The present invention relates in general to a method and an apparatus for controlling clock signals.
Conventional clock signal multiplier circuits are disclosed, for example, in ISSCC Digest of Technical Papers pp. 216-217, February 1996, and U.S. Pat. No. 5,422,835 and U.S. Pat. No. 5,530,837. A typical one of the conventional clock signal multiplier circuits is will be described with reference to FIG. 1. If four times multiplication of the clock signal required, a set of four delay circuits 301, 302, 303 and 304 are provided which are respectively connected to four switch circuits 305, 306, 307 and 308 so that each of the switch circuits 305, 306, 307 and 308 selects one of output terminals of corresponding one of the delay circuits 301, 302, 303 and 304. The four switch circuits 305, 306, 307 and 308 are respectively connected through the four switch circuits 305, 306, 307 and 308 to a single counter 310. The four sets of the delay circuit and the switch circuit ale connected in series to each other. A first clock signal 311 as an external clock signal is inputted into the first delay circuit 301. A second clock signal 312 is outputted from the first switch circuit 305 and inputted into the second delay circuit 302. A third clock signal 313 is outputted from the second switch circuit 306 and inputted into the third delay circuit 303. A fourth clock signal 314 is outputted from the third switch circuit 307 and inputted into the fourth delay circuit 304. A fifth clock signal 315 is outputted from the fourth switch circuit 308 and inputted into a phase comparator 309. The first clock signal is also inputted into the phase comparator 309. The phase comparator 309 receives the first and fifth clock signals 311 and 315 for phase comparison between the first and fifth clock signals 311 and 315. The phase comparator 309 outputs an UP-signal 316 or a DOWN-signal 317 on the basis of the result of the phase comparison between the first and fifth clock signals 311 and 315 and the UP-signal 316 or the DOWN-signal 317 is transmitted to the counter 310. The counter 310 outputs a control signal 318 on the basis of the UP-signal 316 or the DOWN-signal 317. The control signal 318 is transmitted to the four switch circuits 305, 306, 307 and 308 respectively. The control signal is such as to adjust the first and fifth clock signals 311 and 315 to be identical in phase to each other. Delay times of the four delay circuits 301, 302, 303 and 304 are adjusted to be equal to each other, for which reason individual differences in timing are made equal to each other between the first and second clock signals 311 and 312, between the second and third clock signals 312 and 313, and between the third and fourth clock signals 313 and 314. The difference in timing between adjacent two of the four sets of the delay circuit and the switch circuit corresponds to one quarter of a time period of the clock signal. The first clock signal 311, the second clock signal 312, the first clock signal 311 and the fourth clock signal are synthesized in order to obtain a four-time multiplied clock signal.
The clock signal multiplier circuit may comprise a phase lock loop circuit as illustrated in FIG. 2. The clock signal multiplier circuit has a voltage control signal generator 322 and a divider 323 connected to the voltage control signal generator 322 for receiving output signals from the voltage control signal generator 322 to divide the signal. The clock signal multiplier circuit further has a phase comparator 319 connected to the divider 323 for receiving the divided signal from the divider 323 and also receiving an external clock signal 324 in order to conduct a comparison in phase between the divided signal and the external clock signal 324. The phase comparator 319 outputs an UP-signal 325 or a DOWN-signal 326 on the basis of the result of the phase comparison. The clock signal multiplier circuit further has a charge pump circuit 320 connected to the phase comparator 319 for receiving the UP-signal 325 or the DOWN-signal 326 from the phase comparator 319, and a loop filter circuit 321 connected to the charge pump circuit 320 for receiving an output signal from the charge pump circuit 320. The above voltage control signal generator 322 is also connected to the loop filter circuit 321 for receiving an output signal from the loop filter circuit 321 whereby the voltage control signal generator 322 controls a voltage of the signal to be transmitted to the divider 323 on the basis of the received signal from the loop filter circuit 321 so that the divided clock signal is equal in frequency to the external clock signal 324. For this purpose, the voltage control signal generator 322generates a multiplied clock signal 327 which has an inverse multiple to the dividing number.
The first conventional clock signal multiplier circuit as illustrated in FIG. 1 has a disadvantage that it is necessary to make the phase comparison more than several tens of times between the external clock signal and the delayed clock signals supplied through the series connections of the four sets of the delay circuit and the switch circuit, wherein differences in delay and phase are gradually compensated in each comparison process and after the several tens of phase comparison processes have been executed, then it is possible to obtain the multiplied clock signal. This means it difficult for the first conventional clock signal multiplier circuit to exhibit high speed performance.
The second conventional clock signal multiplier circuit as illustrated in FIG. 2 also has a disadvantage that it is necessary to make the phase comparison more than several tens of times between the external clock signal 324 and the divided clock signals supplied through the divider, wherein differences in delay and phase are gradually compensated in each comparison process and after the several tens of phase comparison processes have been executed, then it is possible to obtain the multiplied clock signal. This means it difficult for the second conventional clock signal multiplier circuit to exhibit high speed performances.
For the above first and second conventional clock signal multiplier circuits, it takes a time corresponding to several tens of clocks signals to obtain the required multiplied clock signals.
Further, the above first and second conventional clock signal multiplier circuits are available to control the clock signals but inapplicable as a delay circuit varying signal delay time.
In the above circumstances, it had been required to develop a novel clock signal multiplier circuit free from the above problems.